AALE=Val_0x0, BLEN8=Val_0x0, ONEKBBE=Val_0x0, BLEN4=Val_0x0, AAL=Val_0x0, EN_LPI=Val_0x0, FB=Val_0x0, BLEN16=Val_0x0, LPI_XIT_PKT=Val_0x0
System Bus Mode Register
| FB | Fixed Burst Length When this bit is set to 1, the AXI master initiates burst transfers of specified lengths as given below. Burst transfers of length 1 When this bit is set to 0, the AXI master initiates burst transfers that are equal to or less than the maximum allowed burst length programmed in Bits[3-1]. 0 (Val_0x0): Fixed burst length is disabled 1 (Val_0x1): Fixed burst length is enabled |
| BLEN4 | AXI Burst Length 4 When this bit is set to 1 or the FB bit is set to 0, the AXI master can select a burst length of 4 on the AXI interface. When the FB bit is set to 0, setting this bit has no effect. 0 (Val_0x0): No effect 1 (Val_0x1): AXI burst length 4 |
| BLEN8 | AXI Burst Length 8 When this bit is set to 1 or the FB bit is set to 0, the AXI master can select a burst length of 8 on the AXI interface. When the FB bit is set to 0, setting this bit has no effect. 0 (Val_0x0): No effect 1 (Val_0x1): AXI burst length 8 |
| BLEN16 | AXI Burst Length 16 When this bit is set to 1 or the FB bit is set to 0, the AXI master can select a burst length of 16 on the AXI interface. When the FB bit is set to 0, setting this bit has no effect. 0 (Val_0x0): No effect 1 (Val_0x1): AXI burst length 16 |
| AALE | Automatic AXI LPI enable When set to 1, enables the AXI master to enter into LPI state when there is no activity in the ETH module for number of system clock cycles programmed in the ETH_AXI_LPI_ENTRY_INTERVAL[LPIEI] field. 0 (Val_0x0): Automatic AXI LPI is disabled 1 (Val_0x1): Automatic AXI LPI is enabled |
| AAL | Address-Aligned Beats When this bit is set to 1, the AXI master performs address-aligned burst transfers on Read and Write channels. 0 (Val_0x0): Address-aligned beats is disabled 1 (Val_0x1): Address-aligned beats is enabled |
| ONEKBBE | 1KB Boundary Crossing Enable for the AXI Master When set, the burst transfers performed by the AXI master do not cross 1KB boundary. When reset, the burst transfers performed by the AXI master do not cross 4KB boundary. 0 (Val_0x0): 1KB boundary crossing for the AXI master beats is disabled 1 (Val_0x1): 1KB boundary crossing for the AXI master beats is enabled |
| RD_OSR_LMT | AXI Maximum Read Outstanding Request Limit This value limits the maximum outstanding request on the AXI read interface. Maximum outstanding requests = RD_OSR_LMT + 1. |
| WR_OSR_LMT | AXI Maximum Write Outstanding Request Limit This value limits the maximum outstanding request on the AXI write interface. Maximum outstanding requests = WR_OSR_LMT + 1. |
| LPI_XIT_PKT | Unlock on Magic Packet or Remote Wake-Up Packet When set to 1, this bit enables the AXI master to come out of the LPI mode only when the magic packet or remote wake-up packet is received. When set to 0, this bit enables the AXI master to come out of the LPI mode when any packet is received. 0 (Val_0x0): Unlock on magic packet or remote wake-up packet is disabled 1 (Val_0x1): Unlock on magic packet or remote wake-up packet is enabled |
| EN_LPI | Enable Low Power Interface (LPI) When set to 1, this bit enables the LPI mode and accepts the LPI request from the AXI System Clock controller. When set to 0, this bit disables the LPI mode and always denies the LPI request from the AXI System Clock controller. 0 (Val_0x0): LPI is disabled 1 (Val_0x1): LPI is enabled |